The present invention relates to a solid-state imaging apparatus, and more particularly, to a solid-state imaging apparatus having an exposure control function.
FIG. 1 is a schematic block diagram of a conventional solid-state imaging apparatus 100 and FIG. 2 is a timing waveform chart which describes the operation of the solid-state imaging apparatus 100. The solid-state imaging apparatus 100 includes a CCD image sensor 1, a driver 2, a timing control circuit 3, an integrating circuit 4, a decision circuit 5, an up/down counter 6 and a latch circuit 7.
The CCD image sensor 1 has a plurality of light receiving pixels, a plurality of vertical shift registers and a horizontal shift register. The light receiving pixels are arranged on a light receiving surface in lines at predetermined intervals, and generate and store information charges corresponding to an object image. The vertical shift registers are arranged in columns corresponding to the lines of light receiving pixels, and sequentially transfer the information charges stored in each of the light receiving pixels in the vertical direction. The horizontal shift register is arranged on the output side of the vertical shift registers, receives the information charges output from the vertical shift registers, and outputs the charges in a unit of one line. In this manner, an image signal Y with a changing a voltage value in accordance with the information charges stored in the light receiving pixels is output.
The driver 2 supplies each shift register of the CCD 1 with a multi-phase transfer clock in response to a vertical synchronous signal VD and a horizontal synchronous signal HD from the timing control circuit 3. The driver 2 produces a frame transfer clock φF in response to the vertical synchronous signal VD and supplies the vertical shift register with the frame transfer clock φF. The information charges stored in the light receiving pixels are transferred to the vertical shift registers every vertical scanning period in accordance with the frame transfer clock φF. The driver 2 produces a storage transfer clock φS and a horizontal transfer clock φH in response to the horizontal synchronous signal HD. The vertical shift registers transfer the information charges to the horizontal shift register in accordance with the storage transfer clock φS, and the horizontal shift register outputs the information charges in a unit of one line in accordance with the horizontal transfer clock φH. The driver 2 produces a drain clock φD in response to a shutter timing signal ST from the timing control circuit 3. The drain clock φD is supplied to an unnecessary charge drain region of the CCD 1 and the information charges stored in the light receiving pixels are drained to this drain region. A period L from the end of the drain clock φD to the start of the frame transfer clock φF is defined as the information charges storage period, or the so-called exposure time.
The timing control circuit 3 frequency-divides a reference clock CK having a predetermined period and produces the vertical synchronous signal VD which determines the vertical scan timing of the CCD 1 and the horizontal synchronous signal HD which determines the horizontal scan timing. For example, in conformity with the NTSC (National Television System Committee) standard, the horizontal synchronous signal HD is produced by setting the reference clock CK to 14.32 MHz and frequency-dividing it into 910 parts. The vertical synchronous signal VD is produced by further frequency-dividing the horizontal synchronous signal HD into 252.5 parts.
The integrating circuit 4 integrates the image signal Y output from the CCD 1 in units of a vertical scan periods and produces integration value information IY which is proportional to the average level of the image signal Y. The integrating circuit 4 is reset with the vertical synchronous signal VD.
The decision circuit 5 receives the integration value information IY from the integrating circuit 4, compares the integration value information IY with upper and lower limits which correspond to an appropriate vertical scanning period exposure range, and activates an exposure suppression signal CL or an exposure acceleration signal OP based on the comparison results. If the integration value information IY exceeds the upper limit, the exposure suppression signal CL is activated, and if the integration value information IY is below the lower limit, the exposure acceleration signal OP is activated.
The up/down counter 6 performs an up count operation when the exposure suppression signal CL is activated and performs a down count operation when the exposure acceleration signal OP is activated. A counted value of the up/down counter 6 corresponds to a horizontal scan line number and the timing of the shutter timing signal ST is determined in accordance with the horizontal scan line number.
The latch circuit 7 latches the counted value of the up/down counter 6 every vertical scan period in accordance with the vertical synchronous signal VD and supplies the timing control circuit 3 with the counted value as exposure information D. There are plurality of horizontal scan periods for each vertical scan period. The timing control circuit 3 activates the shutter timing signal ST based on the exposure information D when the horizontal scan period, which corresponds to the counted value of the up/down counter 6, has elapsed from the start of the vertical scanning period. The exposure time L is extended or shortened every vertical scan period in a unit of one horizontal scan period by performing the up count or down count operation in accordance with the integration value information-IY of the image signal Y.
If the level of an image signal is within the range of appropriate exposure, as determined by the decision circuit 5, the exposure time L is not extended or shortened, and system control circuit does not respond to a slight change of luminance of the sensed object. Therefore, a change in the object luminance appears as a change in the image signal. Accordingly, if the brightness of illumination is not stable, the brightness of the illumination appears on a reproduction screen. Further, if a light source which emits light periodically is used, the emission period and imaging period of the light source may substantially coincide. In this case, if a jitter is contained in the emission period of the light source, the average level of the image signal varies due to the jitter. The fluctuation of the average level of such image signal causes a flicker having a long period on the reproduction screen.